1. Field of the Invention
The present invention relates to a semiconductor device having a vertical channel transistor and a method of fabricating the same, and more particularly, to a semiconductor device having a buried bit line formed below a vertical channel transistor, and a method of fabricating the same.
2. Description of the Related Art
With the continued increase in the integration density of semiconductor memory devices, the planar area occupied by each unit cell becomes further reduced. In order to achieve a reduction of the unit cell area, there have been proposed various methods to form a transistor, a bit line, a word line, and a buried contact for a storage node contact of a capacitor, in a limited area. In one of the methods, a semiconductor device with a vertical channel has been proposed, in which a source and a drain are disposed vertically inside an active-region in a semiconductor memory device such as a dynamic random access memory (DRAM), so as to form a vertical channel.
In a vertical channel MOS transistor, the device channel is formed to be oriented in a vertical direction with respect to the primary surface of a semiconductor substrate by forming a gate electrode about an active pillar that extends in a vertical direction with respect to the primary surface of the semiconductor substrate, and forming source/drain regions respectively on and below the active pillar based on the gate electrode. Thus, in this configuration, even though the horizontal device area occupied by the MOS transistor is reduced, the structure of the MOS transistor can be formed without being influenced by channel length. In order to realize the vertical channel semiconductor device as above, a technology of forming a buried bit line structure has been proposed, in which a bit line is buried in an isolation region of a cell.
In order to form the buried bit line in the vertical channel semiconductor device using the conventional technology, the semiconductor substrate is etched using an etch condition in which the buried bit line is self-aligned with the active pillar and an insulating layer is formed about the resulting structure so as to form the buried bit line. The buried bit line formed as above has a problem in that its width is not uniform in the longitudinal direction of the bit line. As a result, the resistance distribution of the bit line becomes non-uniform along its longitudinal direction. Further, in order to perform the self-alignment etch process method to form a line-shaped bit line extending along a predetermined direction, it is restricted to design a plurality of active pillars such that a distance in the direction of the bit line and a distance in the direction perpendicular to the bit line based on each active pillar are different. As a result, alignment design in the x direction and the y direction relative to an active pillar becomes asymmetrical. As such, when semiconductor devices are fabricated by the asymmetrical alignment design layout, an etch process of, for example, etching a conductive layer to form a cylindrical, ring-shaped, gate electrode formed to surround an outer circumference of the active pillar becomes unstable so that an excessive etch can occur in the relatively wider spaces while reduced etching, or lack of etching, can occur in relatively narrow areas, thereby reducing the process margin of the resulting devices. Further, since the space that can be used to form a contact is limited, the process of forming the contact can be complicated.